1. Field
Aspects of the present disclosure relate generally to memory devices, and more particularly, to a process tolerant current leakage reduction in static random access memory (SRAM).
2. Background
Power conservation for memory devices is highly desirable in almost all modern electronics due to such design considerations as length of run-time as well as scalability. Static random-access memory (SRAM) devices are a type of semiconductor memory device that uses bistable latching circuitry to store each bit, which may be referred to as a bitcell or SRAM cell. To reduce power consumption in embedded memory devices such as SRAM devices, modern memory device architectures are typically separated into a core array having one or more memory arrays that include memory banks composed of sets of bitcells, and periphery circuitry that may be used to access specific memory banks. The periphery circuitry includes write and read circuitry to store and recover, respectively, information in a particular memory bank as identified by a decoder. Memory banks that are not being accessed thus only need to be provided with enough power for the bistable latching circuitry in each bitcell to maintain the data stored therein.
SRAM memory devices typically have three different modes of operation. The first mode is an “active” mode in which the core array and the peripheral circuitry are in a ready state, and awaiting an input. In the active mode, a power supply line to each memory array and the peripheral circuitry is held high while a select line to each memory array is held low until an operation needs to be performed. The select line may then be brought high to select a particular memory array. The second mode is a “sleep retention” mode, in which it is desirable for whatever data has been written to the memory arrays to be maintained but for power consumption to be reduced. In the sleep retention mode, the peripheral circuitry is kept off while power is still provided on the power supply line to each memory array. The third mode is a “deep sleep” state, in which both the core array and the peripheral circuitry are turned off and maximum power savings are realized.
Although no power is supplied to the peripheral circuitry and only minimal power is supplied to the core array in the sleep retention mode, the memory device may still suffer power leakage in the core array. This is because any power supplied to core array results in power leakage. One common approach to reduce power leakage is referred to as source voltage biasing, where a supply side voltage is maintained at the same level, but a level for a ground voltage supplied to the memory array, referred to as a source voltage, is raised. Thus, headroom for the memory array, and thus leakage therefrom, is reduced. However, there are some constraints in this approach.
For example, in an SRAM device during the sleep retention mode of operation, the source voltage of the core array is raised to a point just below where it passes rail-to-rail voltage requirement for retaining data. This raised voltage is highly sensitive across process corners. A scheme is needed on top of conventional schemes to converge raised source voltage levels across process corners and to maximize reduction in SRAM core array leakage.